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74F646 * 74F646B * 74F648 Octal Transceiver/Register with 3-STATE Outputs
March 1988 Revised August 1999
74F646 * 74F646B * 74F648 Octal Transceiver/Register with 3-STATE Outputs
General Description
These devices consist of bus transceiver circuits with 3STATE, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers. Data on the A or B bus will be clocked into the registers as the appropriate clock pin goes to a high logic level. Control G and direction pins are provided to control the transceiver function. In the transceiver mode, data present at the high impedance port may be stored in either the A or the B register or in both. The select controls can multiplex stored and real-time (transparent mode) data. The direction control determines which bus will receive data when the enable control G is Active LOW. In the isolation mode (control G HIGH), A data may be stored in the B register and/or B data may be stored in the A register.
Features
s Independent registers for A and B buses s Multiplexed real-time and stored data s 74F648 has inverting data paths s 74F646/74F646B have non-inverting data paths s 74F646B is a faster version of the 74F646 s 3-STATE outputs s 300 mil slim DIP
Ordering Code:
Order Number 74F646SC 74F646MSA 74F646SPC 74F646BSC 74F646BSPC 74F648SC 74F648SPC Package Number M24B MSA24 N24C M24B N24C M24B N24C Package Description 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 24-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
(c) 1999 Fairchild Semiconductor Corporation
DS009580
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74F646 * 74F646B * 74F648
Logic Symbols
74F646/74F646B 74F648
IEEE/IEC 74F646/74F646B
IEEE/IEC 74F648
Connection Diagrams
74F646/74F646B 74F648
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74F646 * 74F646B * 74F648
Unit Loading/Fan Out
Pin Names A0-A7 B0-B7 CPAB, CPBA SAB, SBA G DIR Description Data Register A Inputs/ 3-STATE Outputs Data Register B Inputs/ 3-STATE Outputs Clock Pulse Inputs Select Inputs Output Enable Input Direction Control Input U.L. HIGH/LOW 3.5/1.083 600/106.6 (80) 3.5/1.083 600/106.6 (80) 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 Input IIH/IIL Output IOH/IOL 70 A/-650 A -12 mA/64 mA (48 mA) 70 A/-650 A -12 mA/64 mA (48 mA) 20 A/-0.6 mA 20 A/-0.6 mA 20 A/-0.6 mA 20 A/-0.6 mA
Function Table
Inputs G H H H L L L L L L L L DIR X X X H H H H L L L L CPAB CPBA SAB H or L H or L X SBA X X X X X X X L L H H Output Input Input Input Input Data I/O (Note 1) A0-A7 B0-B7 Isolation Clock An Data into A Register Clock Bn Data into B Register An to Bn--Real Time (Transparent Mode) Output Clock An Data into A Register A Register to Bn (Stored Mode) Clock An Data into A Register and Output to Bn Bn to An--Real Time (Transparent Mode) Clock Bn Data into B Register B Register to An (Stored Mode) Clock Bn Data into B Register and Output to An Function

X X X X X
X X X L L H H X X X X
X X X X X
H or L
H or L

X
H = HIGH Voltage Level L = LOW Voltage Level X = Irrelevant = LOW-to-HIGH Transition
Note 1: The data output functions may be enabled or disabled by various signals at the G and DIR Inputs. Data input functions are always enabled; i.e., data at the bus pins will be stored on every LOW-to-HIGH transition of the clock inputs.
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74F646 * 74F646B * 74F648
Logic Diagrams
74F646/74F646B
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
74F648
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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74F646 * 74F646B * 74F648
Absolute Maximum Ratings(Note 2)
Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias VCC Pin Potential to Ground Pin Input Voltage (Note 3) Input Current (Note 3) Voltage Applied to Output in HIGH State (with VCC = 0V) Standard Output 3-STATE Output Current Applied to Output in LOW State (Max) ESD Last Passing Voltage (Min) twice the rated IOL (mA) 4000V -0.5V to VCC -0.5V to +5.5V -65C to +150C -55C to +125C -55C to +150C -0.5V to +7.0V -0.5V to +7.0V -30 mA to +5.0 mA
Recommended Operating Conditions
Free Air Ambient Temperature Supply Voltage 0C to +70C +4.5V to +5.5V
Note 2: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 3: Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Symbol VIH VIL VCD VOH VOL IIH IBVI IBVIT ICEX VID IOD IIL IIH + IOZH IIL + IOZL IOS IZZ ICCH ICCL ICCZ Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Current Input HIGH Current Breakdown Test Input HIGH Current Breakdown (I/O) Output HIGH Leakage Current Input Leakage Test Output Leakage Circuit Current Input LOW Current Output Leakage Current Output Leakage Current Output Short-Circuit Current Bus Drainage Test Power Supply Current Power Supply Current Power Supply Current -100 4.75 3.75 -0.6 70 -650 -225 500 135 150 150 10% VCC 10% VCC 2.0 0.55 5.0 7.0 0.5 50 Min 2.0 0.8 -1.2 Typ Max Units V V V V V A A mA A V A mA A A mA A mA mA mA Min Min Min Max Max Max Max 0.0 0.0 Max Max Max Max 0.0V Max Max Max VCC Conditions Recognized as a HIGH Signal Recognized as a LOW Signal IIN = -18 mA (Non I/O Pins) IOH = -15 mA (An, Bn) IOL = 64 mA (A n, Bn) VIN = 2.7V (Non I/O Pins) VIN = 7.0V (Non I/O Pins) VIN = 5.5V (An, Bn) VOUT = VCC IID = 1.9 A All Other Pins Grounded VIOD = 150 mV All Other Pins Grounded VIN = 0.5V (Non I/O Pins) VOUT = 2.7V (An, Bn) VOUT = 0.5V (An, Bn) VOUT = 0V VOUT = 5.25V VO = HIGH VO = LOW VO = HIGH Z
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AC Electrical Characteristics 74F646/74F648
TA = +25C Symbol Parameter VCC = +5.0V CL = 50 pF Min fMAX tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ tPZH tPZL tPHZ tPLZ Maximum Clock Frequency Propagation Delay Clock to Bus Propagation Delay Bus to Bus (74F646) Propagation Delay Bus to Bus (74F648) Propagation Delay SBA or SAB to A or B Enable Time OE to A or B Disable Time OE to A or B Enable Time DIR to A or B Disable Time DIR to A or B 90 2.0 2.0 1.0 1.0 2.0 1.0 2.0 2.0 2.0 2.0 1.0 2.0 2.0 2.0 1.0 2.0 7.0 8.0 7.0 6.5 8.5 7.5 8.5 8.0 8.5 12.0 7.5 9.0 14.0 13.0 9.0 11.0 Max TA = -55C to +125C VCC = +5.0V CL = 50 pF Min 75 2.0 2.0 1.0 1.0 1.0 1.0 2.0 2.0 2.0 2.0 1.0 2.0 2.0 2.0 1.0 2.0 8.5 9.5 8.0 8.0 10.0 9.0 11.0 10.0 10.0 13.5 9.0 11.0 16.0 15.0 10.0 12.0 Max TA = 0C to +70C VCC = +5.0V CL = 50 pF Min 90 2.0 2.0 1.0 1.0 2.0 1.0 2.0 2.0 2.0 2.0 1.0 2.0 2.0 2.0 1.0 2.0 8.0 9.0 7.5 7.0 9.0 8.0 9.5 9.0 9.0 12.5 8.5 9.5 15.0 14.0 9.5 11.5 Max MHz ns ns ns ns ns Units
ns ns ns
AC Operating Requirements 74F646/74F648
TA = +25C Symbol Parameter VCC = +5.0V Min tS(H) tS(L) tH(H) tH(L) tW(H) tW(L) Setup Time, HIGH or LOW Bus to Clock Hold Time, HIGH or LOW Bus to Clock Clock Pulse Width HIGH or LOW 5.0 5.0 2.0 2.0 5.0 5.0 Max TA = -55C to +125C VCC = +5.0V Min 5.0 5.0 2.5 2.5 5.0 5.0 Max TA = 0C to +70C VCC = +5.0V Min 5.0 5.0 2.0 2.0 5.0 5.0 Max ns ns ns Units
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74F646 * 74F646B * 74F648
AC Electrical Characteristics 74F646B
TA = +25C Symbol Parameter VCC = +5.0V CL = 50 pF Min fMAX tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ tPZH tPZL tPHZ tPLZ Maximum Clock Frequency Propagation Delay Clock to Bus Propagation Delay Bus to Bus Propagation Delay SBA or SAB to A or B Enable Time OE to A or B Disable Time OE to A or B Enable Time DIR to A or B Disable Time DIR to A or B 165 2.5 3.0 2.0 2.0 2.5 2.5 2.5 2.5 1.5 2.0 2.0 3.0 1.5 2.5 7.0 7.5 6.0 6.0 7.5 7.5 6.5 9.0 6.5 7.0 7.0 9.5 7.5 8.5 Max TA = -55C to +125C VCC = +5.0V CL = 50 pF Min Max TA = 0C to +70C VCC = +5.0V CL = 50 pF Min 150 2.5 3.0 2.0 2.0 2.5 2.5 2.5 2.5 1.5 2.0 2.0 3.0 1.5 2.5 8.0 8.0 7.0 7.0 8.5 8.5 8.0 10.0 7.5 8.5 8.5 10.0 8.5 9.5 Max MHz ns ns ns ns Units
ns ns ns
AC Operating Requirements 74F646B
TA = +25C Symbol Parameter VCC = +5.0V Min tS(H) tS(L) tH(H) tH(L) tW(H) tW(L) Setup Time, HIGH or LOW Bus to Clock Hold Time, HIGH or LOW Bus to Clock Clock Pulse Width HIGH or LOW 5.0 5.0 1.5 1.5 5.0 5.0 Max TA = -55C to +125C VCC = +5.0V Min Max TA = 0C to +70C VCC = +5.0V Min 4.0 4.0 1.5 1.5 5.0 5.0 Max ns ns ns Units
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74F646 * 74F646B * 74F648
Physical Dimensions inches (millimeters) unless otherwise noted
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M24B
24-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide Package Number MSA24
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74F646 * 74F646B * 74F648 Octal Transceiver/Register with 3-STATE Outputs
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide Package Number N24C
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 9 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com
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